The present invention relates to a semiconductor device having a built-in self-test (BIST) circuit for testing an external memory, and to a technique effective when applied to a semiconductor device in system-on-chip form and a semiconductor device in system-in-package form having mounted therein a memory chip along with a data processor in system-on-chip form.
In a prior art search conducted after the completion of the present invention, the following known documents are found. Japanese Unexamined Patent Publication No. 2004-093433 describes a technique for directly performing the operation test of a flash memory using a TAP (Test Access Port) controller. Test information such as a command and an address is directly provided to the flash memory through the use of a scan chain in which input/output is controlled by the TAP controller. Japanese Unexamined Patent Publication No. 2005-332555 describes a BIST circuit for carrying out performance comparison of an SDRAM to be tested, in which a test pattern is generated based on control information inputted through the use of a TAP controller and supplied to the SDRAM, and an output from the SDRAM is inputted to the BIST circuit. Japanese Unexamined Patent Publication No. Hei10 (1998)-069800 describes a semiconductor integrated circuit having a test circuit for refreshing a memory circuit during testing.